The present invention relates to semiconductor device manufacturing and processing techniques, and more particularly to the formation of lateral extensions in metal oxide semiconductor field effect transistors (MOSFETs).
Over the last several decades, semiconductor device manufacturers have expended considerable effort in reducing the size (scale) of integrated MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) devices while simultaneous increasing their speed and reducing power consumption. With each new generation of scaled (reduced size) MOSFET devices, speed and density are increased, and power consumption is reduced.
In order to support continued scaling (reductions in size) of MOSFET devices, however, series resistance of the devices (including the resistance of lateral extensions of the source and drain), must be reduced at each generation. Without such a reduction in series resistance, scaling of the transistor channel produces diminishing returns in overall device performance, as series resistance (rather than transistor channel resistance) becomes a dominant factor in limiting drive current (ION).
Typically, source and drain regions in a modern MOSFET device are formed of suicides (e.g., Cobalt Silicide CoSi2, Nickel Silicide—NiSi, Titanium Silicide—TiSix). Silicides are commonly used as conductors and contact materials in silicon semiconductor technology due to their very high conductivity, compatibility with silicon, and suitability to small-geometry semiconductor devices. The high conductivity (low resistivity) of source/drain silicide serves to minimize the contribution of parasitic resistance in the source drain region to the series resistance of MOSFET devices that employ it. The parasitic series resistance of silicide itself is often so small that its contribution to total series resistance is considered to be negligible and not a limiting factor to device performance.
The series resistance of a typical MOSFET device is the sum of source/drain silicide contact resistance (between the silicide and doped silicon), extension resistance, and spreading resistance between the extension and the channel. In order to minimize lateral extension resistance, the extensions are made very short. A typical lateral extension is formed as a shallow doped region having electrical conductivity substantially lower than that of a typical silicide. A typical extension depth in a modern MOSFET device is less than about 50 nm and could be as shallow as 10 nm. Due to the combined effects of relatively low electrical conductivity and relatively shallow depth, a lateral extension may introduce a substantial series resistance, thereby impeding current flow through the transistor. For this reason, the extension is made as short as possible. However, if the extensions are too short, the source/drain silicide may penetrate through the extension and come into direct contact with the channel and the effective contact resistance between the silicide and the channel will become very high due to a relatively low channel carrier concentration and the resultant wide Schottky barrier. Further, the silicide may come into a direct contact with the transistor body creating leakage and increasing circuit power consumption.
Ideally, a thin, highly-doped layer (extension) between the source/drain silicide and the channel would reduce effective contact resistance to acceptable levels by providing a suitable transition interface between the silicide and the channel, thereby substantially eliminating the negative effects of the aforementioned wide Schottky barrier and increased leakage due to the direct contact between the silicide and transistor body.
Conventional processing techniques, however, present a significant obstacle to the formation of a thin, highly-doped layer between the silicide extensions and the channel. By way of example: one approach to forming such a highly-doped layer is to provide very thin nitride spacers around the gate, then to perform silicidation at the extension region. A problem with this technique is that the silicide forms under the spacer due to the generally isotropic nature of the diffusion processes of intermixing silicon and metal atoms. Further, the silicide/silicon interface is usually non-uniform due to “spiking” of the silicide into the silicon beyond the boundary defined by ideal isotropic diffusion processes. Further still, the lateral “roughness” of the silicide can be considerable due to a variety of factors that promote silicide growth under the spacer. Examples of such factors include: preferred growth of the silicide along certain crystal orientations, preferred growth of the suicide in locally stressed areas, and/or preferred growth of the silicide in areas of high silicon crystal defect concentration. These factors present a high probability that the silicide will breach the thin, highly-doped layer and come into direct contact with the channel, effectively increasing the contact resistance of the silicide extensions and the channel and negating the beneficial effect of the thin, highly-doped layer.
If the thickness of the highly-doped layer is increased sufficiently that the probability of the silicide coming into direct contact with the channel is low, then the series resistance of the layer is increased.
In light of the foregoing, it would be desirable to provide a structure and method for reliably forming thin, highly-doped layers between source/drain silicide and a MOSFET channel region without risk of breach by the silicide.